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DSP56857 bảng dữ liệu(PDF) 553 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 553 Page - Freescale Semiconductor, Inc |
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553 / 662 page ![]() Application: Date: Programmer: Sheet Appendix B - Programmer’s Sheets, Rev. 4 Freescale Semiconductor B-51 7 of 8 DMA DMA Transfer Control Register (DMATC) Bits Name Description 15 DMAON Direct Memory Access On This bit enables/disables the DMA operation. 0 DMA operation is disabled 1 DMA operation is enabled 14 INTRON Interrupt On This bit enables/disables the DMA interrupt operation 0 DMA interrupt operation is disabled 1 DMA interrupt operation is enabled 13 INTRPEND Interrupt Pending This is the DMA interrupt pending bit 0 DMA interrupt is not pending 1 DMA interrupt is pending 12 DATASIZE Data Size This bit defines the data size of the DMA transfers 0 DMA transfers are performed in bytes (8 bits) 1 DMA transfers are performed in words (16 bits) DMA Transfer Control Register (DMATC) Base + $0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DMA_ON INTR_ON INTR_PEND DATA_SIZE 0 0 0 PERIPH SEL SS/M DS/M Write 0 0 0 Reset 0 0 0 0 0 0 0 00000 0 0 0 0 denotes Reserved Bits See the following page for continuation of this register |
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