DSP56857 datasheet(514/662 Pages) FREESCALE

514 / 662 page

Application:

Date:

Programmer:

Sheet

5685X Digital Signal Controller User Manual, Rev. 4

B-12

Freescale Semiconductor

3 of 4

EMI

Chip Select Timing Control Registers (CSTC0–3)

Chip Select

Timing Control

(CSTC0-CSOR3)

$1FFE40 + $10-$13

Bits

Read

WWSS

WWSH

RWSS

RWSH

MDAR

Write

Reset

0000000

000

0011

Bits

Name

Description

15 - 14

WWSS

Write Wait States Setup Delay

This field affects the write cycle timing diagram, illustrated in Figure 5-16. Additional time

(clock cycles) is provided between the assertion of CSn and address lines and the assertion

of WR. The value of WWSS should be set as indicated in Section 5.7.2.

13 - 12

WWSH

Write Wait States Hold Delay

This field affects the write cycle timing diagram, illustrated in Figure 5-17. The WWSH field

specifies the number of additional system clocks to hold the address, data, and CSn signals

after the WR signal is deasserted. The value of WWSH should be set as indicated in

Section 5.7.2.

11 - 10

RWSS

Read Wait States Setup Delay

This field affects the read cycle timing diagram, illustrated in Figure 5-10. Additional time

(clock cycles) is provided between the assertion of CSn and address lines and the assertion

of RD. The value of RWSS should be set as indicated in Section 5.7.1.

9 - 8

RWSH

Read Wait States Hold Delay

This field affects the read cycle timing diagram, illustrated in Figure 5-11. The RWSH field

specifies the number of additional system clocks to hold the address, data, and CSn signals

after the RD signal is deasserted. The value of RWSH should be set as indicated in

Section 5.7.1.

2 - 0

MDAR

Minimal Delay After Read

This field specifies the number of system clocks to delay between reading from memory in

a CSn controlled space and reading from another device. Since a write to the device implies

activating the device on the bus, this is also considered a read from another device.

Figure 5-6 illustrates the timing issue requiring the introduction of the MDAR field. In this

diagram, CS1 is assumed to operate a slow flash memory in P-space while CS2 is operating

a faster RAM in X-space. In some bus contention cases, it is possible to encounter data

integrity problems where the contention is occurring at the time the data bus is sampled.

denotes Reserved Bits

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