DSP56857 datasheet(513/662 Pages) FREESCALE

513 / 662 page

Application:

Date:

Programmer:

Sheet

Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-11

2 of 4

EMI

Chip Select Option Register (CSOR0-3)

Chip Select

Option Register

(CSOR0-CSOR3)

$1FFE40 + $8-$B

Bits

Read

RWS

BYTE_EN

R/W

PS/DS

WWS

Write

Reset

1110000

001

0111

Bits

Name

Description

9 - 8

BYTE_EN

Upper/Lower Byte Enable (UBS and LBS)

Accesses to external data memory are typically through the use of a word. For data memory

access, the 56800 core can also access bytes, yielding the upper and lower half of a word.

CSOR Encoding of CS UBS Functionality

CSOR Encoding of CS LBS Functionality

Disabled

Lower Byte Enabled

Upper Byte Enabled

Both Bytes Enabled

Both Bytes are Enabled

7 - 6

R/W

Read/Write

The chip select will be disabled

The chip select will be enabled for both read/write

The chip select will allow read only

The chip select will allow read/write

5 - 4

PS/DS

Program/Data Space Select

The chip select will be disabled

The chip select will allow Data Space only

The chip select will allow Program Space only

The chip select will be enabled

3 - 0

WWS

Write Wait State

Specifies minimum number of IPBus_CLK Wait states required by an EMI access.

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