DSP56857 datasheet(405/662 Pages) FREESCALE

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Module Memory Maps

General Purpose Input/Output (GPIO), Rev. 4

Freescale Semiconductor

15-5

15.6 GPIO Configurations

Each GPIO port is controlled by the registers listed in Table 15-1. Each register bit corresponds

to a GPIO pin. Section 15-1 illustrates the logic associated with one GPIO bit.

15.7 Module Memory Maps

There are eight GPIO mapped modules listed in the following in tables, Table 15-2 through

Table 15-9 and their individual accompanying register maps. The GPIO peripherals are

summarized in Figure 15-2 through Figure 15-9.

Table 15-1. GPIO Registers Functions

Description

Function

PER

Peripheral Enable Register

Determines if pin functions as GPIO or associated peripheral pin

DDR

Data Direction Register

Determines pin direction (input or output) when pin functions as GPIO

Data Register

Data interface between the GPIO pin and the IPBus

PUER

Pull-up Enable Register

Enables internal pull-up, qualified by other factors

Table 15-2. GPIO A Memory Map (GPIOA_BASE = $1FFE60)

Address Offset

Access Type

Chapter Location

Base + $0

GPIO_A_PER

Peripheral Enable Register

Read/Write

Section 15.8.1

Base + $1

GPIO_A_DDR

Data Direction Register

Read/Write

Section 15.8.9

Base + $2

GPIO_A_DR

Data Register

Read/Write

Section 15.8.17

Base + $3

GPIO_A_PUR

Pull-Up Enable Register

Read/Write

Section 15.8.25

Add.

Offset

9876

54321

PER

DDR

DATA

PUR

PUE

Read as 0

Reserved

Figure 15-2. GPIO A Register Map Summary

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