DSP56857 datasheet(350/662 Pages) FREESCALE

350 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-50

Freescale Semiconductor

12.8.10.12 Serial Output Flag 0 (OF0)—Bit 0

When SC0 is configured for Output Flag functionality, provided in Table 12-16, this control bit

determines the state of the output pin. Changes in the OF0 bit will appear on the SC0 pin at the

beginning of the next frame in the Normal mode, or at the beginning of the next time slot in the

Network mode.

12.8.11 ESSI Transmit and Receive Control Registers (STXCR, SRXCR)

The STXCR and SRXCR are 16-bit, read/write control registers used to direct the operation of

the ESSI. These registers control the ESSI clock generator bit and frame sync rates, word length,

and number of words per frame for the serial data. Please refer to Figure 12-35 to better

understand how these fields are used in the clock generators.

The STXCR register is dedicated to the transmit section. The SRXCR register is dedicated to the

receive section, except in the Synchronous mode where the STXCR register controls both the

receive and transmit sections.

Power-On Reset (POR) clears all STXCR and SRXCR bits. The ESSI reset (ESSIEN = 0) does

not affect the STXCR and SRXCR bits. The control bits are described in the ESSI Transmit

Control Register (STXCR).

Figure 12-25. ESSI Transmit Control Register (STXCR)

See Programmer’s Sheet on Appendix page B - 78

Figure 12-26. ESSI Receive Control Register (SRXCR)

See Programmer’s Sheet on Appendix page B - 78

Base + $8

Read

PSR

Write

Reset

Base + $9

Read

PSR

Write

Reset

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