DSP56857 datasheet(348/662 Pages) FREESCALE

348 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-48

Freescale Semiconductor

12.8.10.3 Transmit Status Flag Control 1 (TXSF1)—Bit 9

•

0 = The indicated transmitter does not affect the status bits.

•

1 = The indicated transmitter status will affect the TFF, TDE, TUE, and TFE status bits.

The status from all selected transmitters is ORed to create the register status bit. These bits

should be set to match the intended operation of the TE0, TE1, and TE2 control bits.

12.8.10.4 Transmit Status Flag Control 2 (TXSF2)—Bit 8

•

0 = The indicated transmitter does not affect the status bits.

•

1 = The indicated transmitter status will affect the TFF, TDE, TUE, and TFE status bits.

The status from all selected transmitters is ORed to create the register status bit. These bits

should be set to match the intended operation of the TE0, TE1, and TE2 control bits.

12.8.10.5 Reserved—Bit 7

This bit is reserved or not implemented. It is read as, and written with a 0.

12.8.10.6 Select SC1 (SSC1)—Bit 6

This bit controls the functionality of the SC1 signal. This control bit is used only if

SYN = 1

and TE2 = 0.

•

0 = The SC1 acts as the serial I/O flag (IF1/OF1).

•

1 = When configured as an output (SCD1 = 1), the SC1 signal acts as the transmitter 0

driver-enable, enabling an external buffer for the transmitter 0 output.

Note:

If SSC1 = 1 and SCD1 = 0, the configuration is invalid.

12.8.10.7 Clock Source Direction (SCKD)—Bit 5

This bit configures the source of the clock signal used to clock the Transmit Shift register in

Asynchronous mode and both Transmit and Receive Shift registers are in Synchronous mode.

•

0 = SCK pin is configured as an input. This pin is used as the clock source.

•

1 = Internal transmit clock generator is selected. This clock is output on the SCK pin.

12.8.10.8 Serial Control Direction 2 (SCD2)—Bit 4

This bit controls the direction of the SC2 pin.

•

0 = SC2 is an input.

•

1 = SC2 is an output.

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