DSP56857 datasheet(339/662 Pages) FREESCALE

339 / 662 page

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-39

If the transmit FIFO is disabled:

•

0 = No interrupt is generated.

•

1 = An interrupt is generated when the TDE flag in the SSR is set. One value can be

written to each of the enabled STX0-2 registers when this interrupt occurs.

If the transmit FIFO is enabled:

•

0 = No interrupt is generated.

•

1 = An interrupt is generated when the TFE flag in the SSR is set. When this interrupt

occurs, up to eight values can be written to each of the enabled STX0-2 registers,

depending on the level of the TXFIFO watermark.

The TDE bit always indicates the STX register empty condition even when the transmitter is

disabled by the Transmit Enable (TE) bits in the SCR2. Writing data to the STX register or STSR

clears the TDE bit, thus clearing the interrupt. Two transmit data interrupts with separate

interrupt vectors are available:

1. Transmit data with exception status

2. Transmit data without exceptions

12.8.8.3 Table 12-14 lists the conditions these interrupts are generated.

12.8.8.4 Receive Enable (RE)—Bit 13

This control bit enables the receive portion of the ESSI.

•

0 = Receiver is disabled by inhibiting data transfer into the SRX. If data is being received

when this bit is cleared, the rest of the word is not shifted in, or is it transferred to the SRX

•

1 = Receive portion of the ESSI is enabled and received data will be processed starting

with the next receive frame sync.

If the RE bit is re-enabled during a time slot before the second to last bit, then the word will be

received. It is recommended to clear this bit when clearing ESSIEN.

Table 12-14.

ESSI Transmit Data Interrupts 1

Table 12-27 provides a complete list of interrupts.

Interrupt

TIE

Selection Control

TUE

TFEN = 0

TFEN = 1

Transmit Data with Exception Status

TDE = 1

TFE = 1

Transmit Date without Exception Status

TDE = 1

TFE = 1

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