DSP56857 datasheet(342/662 Pages) FREESCALE

342 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-42

Freescale Semiconductor

Note:

The codec device labels the MSB as bit 0, whereas the ESSI labels the LSB as bit 0.

Therefore, when using a standard codec, the ESSI MSB (or codec bit 0) is shifted out

first, and the TSHFD bit should be cleared.

12.8.8.11 Transmit Clock Polarity (TSCKP)—Bit 5

This control bit determines which bit clock edge is used to clock out data in the transmit section.

•

0 = Data is clocked out on the rising edge of the bit clock.

•

1 = The falling edge of the bit clock is used to clock the data out.

12.8.8.12 ESSI Enable (ESSIEN)—Bit 4

This control bit enables and disables the ESSI.

•

0 = The ESSI is disabled and held in a reset condition. When disabled, all output pins are

tri-stated, the status register bits are preset to the same state produced by the Power-On

Reset (POR) and the Control register bits are unaffected. The contents of the STX,

TXFIFO and RXFIFO are cleared when this bit is reset. When ESSI is disabled, all

internal clocks are disabled except clocks required for register access. When clearing

ESSIEN, it is recommended to also clear RE and TE0-2.

•

1 = The ESSI is enabled, causing an output frame sync to be generated when set up for

internal frame sync, or it causes the ESSI to wait for the input frame sync when set up for

external frame sync.

12.8.8.13 Network Mode (NET)—Bit 3

This control bit selects the operational mode of the ESSI.

•

0 = Normal mode is selected.

•

1 = Network mode is selected.

12.8.8.14 Transmit Frame Sync Invert (TFSI)—Bit 2

This control bit selects the logic of frame sync I/O.

•

0 = Frame sync is active high

•

1 = Frame sync is active low

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