DSP56857 datasheet(337/662 Pages) FREESCALE

337 / 662 page

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-37

12.8.7.16 Transmit FIFO Empty (TFE)—Bit 0

This flag bit is set when the transmit section is programmed with an enabled TXFIFO and the

data level in the TXFIFO falls below the selected Transmit FIFO Watermark (TFWM) threshold.

When set, the TFE bit indicates data can be written to the TXFIFO register. The TFE bit is

cleared by writing data to the STX register until the TXFIFO data content level reaches the water-

mark level.

Note:

An interrupt is generated only if both TFE and the TIE bits are set if a transmit FIFO is

enabled.

The TFE bit is set by Power-On Reset (POR) and when ESSI is disabled (ESSIEN = 0).

12.8.8 ESSI Control Register 2 (SCR2)

The ESSI Control Register 2 (SCR2) is one of five 16-bit, read/write control registers used to

direct the operation of the ESSI. The ESSI reset is controlled by a bit in SCR2. Interrupt enable

bits for the receive and transmit sections are provided in this control register. ESSI operating

modes are also selected in this register.

The Power-On Reset (POR) clears all SCR2 bits. The ESSI reset (ESSIEN = 0) does not affect

the SCR2 bits. The SCR2 bits are described in the following paragraphs.

Note:

As with all on-chip peripheral interrupts, the interrupt controller must be configured to

allow ESSI maskable interrupts and determine their interrupt priority level, before

enabling them in this register.

Figure 12-22. ESSI Control Register 2 (SCR2)

See Programmer’s Sheet on Appendix page B - 72

Base + $5

Read

RIE

TIE

TE0

TE1

TE2

SYN TSHFD TSCKP ESSIEN

NET

TFSI TFSL TEFS

Write

Reset

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