DSP56857 datasheet(209/662 Pages) FREESCALE

209 / 662 page

Overview, Rev. 4

Freescale Semiconductor

8-31

•

01 = Required nested exception priority levels are 1, 2, or 3

•

10 = Required nested exception priority levels are 2 or 3

•

11 = Required nested exception priority level is 3

8.7.16.3 Vector Number (VAB)—Bits 12–6

This bit field shows the Vector Number, described in Table 8-3 of the last IRQ taken. This bit

field is only updated when the 56800E core jumps to a new interrupt service routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt

service routine can read it.

8.7.16.4 Interrupt Disable (INT_DIS)—Bit 5

This bit allows the user to disable all interrupts.

•

0 = Normal operation (default)

•

1 = All interrupts disabled

8.7.16.5 Reserved—Bit 4

This bit is reserved or not implemented. It is read as 0, but they cannot be modified by writing.

8.7.16.6 State of IRQB (IRQB STATE)—Bit 3

This bit reflects the state of the external IRQB pin.

8.7.16.7 State of IRQA (IRQA STATE)—Bit 2

This bit reflects the state of the external IRQA pin.

8.7.16.8 IRQB Edge (IRQB EDG)—Bit 1

This bit controls whether the external IRQB interrupt is edge or level sensitive. During Stop and

Wait modes it is automatically level sensitive.

•0 = IRQB interrupt is low level sensitive (default)

•1 = IRQB interrupt is falling edge sensitive

8.7.16.9 IRQA Edge (IRQA EDG)—Bit 0

This bit controls whether the external IRQA interrupt is edge or level sensitive. During Stop and

Wait modes it is automatically level sensitive.

•0 = IRQA interrupt is low level sensitive (default)

•1 = IRQA interrupt is falling edge sensitive

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