MB91460C datasheet(22/106 Pages) CYPRESS

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Document Number: 002-04609 Rev. *A

Page 22 of 106

MB91460C Series

6. Notes on Debugger

6.1 Execution of the RETI Command

If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine

will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority

level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will

always break on the first line of the time-base timer interrupt handler).

Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging.

6.2 Break function

If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer

or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually

contains data access instructions.

To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware

break (including an event breaks).

6.3 Operand break

It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the

areas containing the address of system stack pointer as a target of data event break.

6.4 Notes on PS register

As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may result

in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, the operation before

and after the EIT always proceeds according to specification.

The following behavior may occur if any of the following occurs in the instruction immediately after a

DIV0U/DIV0S instruction:

a. a user interrupt or NMI is accepted;

b. single-step execution is performed;

c. execution breaks due to a data event or from the emulator menu.

1. D0 and D1 flags are updated in advance.

2. An EIT handling routine (user interrupt/NMI or emulator) is executed.

3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed

and the D0 and D1 flags are updated to the same values as those in 1.

The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user

interrupt or NMI source while that interrupt is in the active state.

1. The PS register is updated in advance.

2. An EIT handling routine (user interrupt/NMI or emulator) is executed.

3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1.

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