MB91460C datasheet(73/106 Pages) CYPRESS

73 / 106 page

Document Number: 002-04609 Rev. *A

Page 73 of 106

MB91460C Series

Notes:

*1: The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request.

An ICR is provided for each interrupt request.

*2:The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value

(TBR). The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value

(0x000FFC00). The TBR is initialized to this value by a reset. After execution of the internal boot ROM TBR is set to 0x000FFC00.

*3: Used by REALOS

*4: ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0x0C03 : IOS[0])

*5: System reserved

*6: Memory Protection Unit (MPU) support

Low Voltage Detection

138

ICR61

0x47D

0x1D4

0x000FFDD4

Reserved

139

0x1D0

0x000FFDD0

Timebase Overflow

140

ICR62

0x47E

0x1CC

0x000FFDCC

PLL Clock Gear

141

0x1C8

0x000FFDC8

DMA Controller

142

ICR63

0x47F

0x1C4

0x000FFDC4

Main/Sub OSC stability wait

143

0x1C0

0x000FFDC0

Security vector

144

0x1BC

0x000FFDBC

Used by the INT

instruction.

145

255

0x1B8 to

0x000

0x000FFDB8

0x000FFC00

Interrupt

number

Interrupt level *1

Interrupt vector *2

DMA

Resource

number

Decimal

Hexa-

decimal

Setting

address

Offset

Default Vector

address

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