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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HT67F5652 bảng dữ liệu(PDF) 161 Page - Holtek Semiconductor Inc |
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HT67F5652 bảng dữ liệu(HTML) 161 Page - Holtek Semiconductor Inc |
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161 / 224 page  Rev. 1.00 1�0 De�e��e� 0�� �01� Rev. 1.00 1�1 De�e��e� 0�� �01� HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU Baud Rate K/BPS Baud Rates for BRGH=1 fSYS=4MHz fSYS=3.579545MHz fSYS=7.159MHz BRG Kbaud Error (%) BRG Kbaud Error (%) BRG Kbaud Error (%) 0.3 — — — — — — — — — 1.� �0� 1.�0� 0.1� 185 1.�03 0.�3 — — — �.4 103 �.404 0.1� 9� �.40� 0.�3 185 �.40� 0.�3 4.8 51 4.808 0.1� 4� 4.�� -0.83 9� 4.811 0.�3 9.� �5 9.�15 0.1� �� 9.��� 1.3� 4� 9.5�0 -0.83 19.� 1� 19.�31 0.1� 11 18.�43 -�.90 �� 19.454 1.3� 38.4 � 35.�14 -�.99 5 3�.�8� -�.90 11 3�.�8� -�.90 5�.� 3 ��.5 8.51 3 55.930 -�.90 � 55.930 -�.90 115.� 1 1�5 8.51 1 111.8� -�.90 3 111.8� -�.90 �50 0 �50 0 — — — — — — Baud Rates and Error Values for BRGH = 1 UART Setup and Control Fordatatransfer,theUARTfunctionutilizesanon-return-to-zero,morecommonlyknownasNRZ, format.Thisiscomposedofonestartbit,eightorninedatabits,andoneortwostopbits.Parity issupportedbytheUARThardware,andcanbesetuptobeeven,oddornoparity.Forthemost commondataformat,8databitsalongwithnoparityandonestopbit,denotedas8,N,1,isused asthedefaultsetting,whichisthesettingatpower-on.Thenumberofdatabitsandstopbits,along withtheparity,aresetupbyprogrammingthecorrespondingBNO,PRT,PREN,andSTOPSbits intheUCR1register.Thebaudrateusedtotransmitandreceivedataissetupusingtheinternal 8-bitbaudrategenerator,whilethedataistransmittedandreceivedLSBfirst.AlthoughtheUART transmitterandreceiverarefunctionallyindependent,theybothusethesamedataformatandbaud rate.Inallcasesstopbitswillbeusedfordatatransmission. Enabling/Disabling the UART Thebasicon/offfunctionoftheinternalUARTfunctioniscontrolledusingtheUARTENbitinthe UCR1register.IftheUARTEN,TXENandRXENbitsareset,thenthesetwoUARTpinswillact asnormalTXoutputpinandRXinputpinrespectively.IfnodataisbeingtransmittedontheTX pin,thenitwilldefaulttoalogichighvalue. ClearingtheUARTENbitwilldisabletheTXandRXpinsandallowthesetwopinstobeusedas normalI/Oorotherpin-sharedfunctionalpins.WhentheUARTfunctionisdisabledthebufferwill beresettoanemptycondition,atthesametimediscardinganyremainingresidualdata.Disabling theUARTwillalsoresettheerrorandstatusflagswithbitsTXEN,RXEN,TXBRK,RXIF,OERR, FERR,PERRandNFbeingclearedwhilebitsTIDLE,TXIFandRIDLEwillbeset.Theremaining controlbitsintheUCR1,UCR2andBRGregisterswillremainunaffected.IftheUARTENbitin theUCR1registerisclearedwhiletheUARTisactive,thenallpendingtransmissionsandreceptions willbeimmediatelysuspendedandtheUARTwillberesettoaconditionasdefinedabove.Ifthe UARTisthensubsequentlyre-enabled,itwillrestartagaininthesameconfiguration. |
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