HT67F5652 datasheet(17/224 Pages) HOLTEK

17 / 224 page

Rev. 1.00

1�

De�e��e� 0�� 01�

Rev. 1.00

1�

De�e��e� 0�� 01�

HT67F5652

24-Bit Delta Sigma A/D + LCD Flash MCU

HT67F5652

24-Bit Delta Sigma A/D + LCD Flash MCU

Symbol

Parameter

Test Conditions

Min. Typ. Max.

Unit

VDD

Conditions

VDROP_LDO LDO D�opout Voltage(Note�)

—

LDOVS[1:0]=00B�

VIN=3.�V� ILOAD=10�A�

∆VOUT_LDO=�%

—

100

�V

LDOVS[1:0]=01B�

VIN=3.�V� ILOAD=10�A�

∆VOUT_LDO=�%

—

130

LDOVS[1:0]=10B�

VIN=3.�V� ILOAD=10�A�

∆VOUT_LDO=�%

—

180

LDOVS[1:0]=11B�

VIN=3.�V� ILOAD=10�A�

∆VOUT_LDO=�%

—

�00

TCLDO

LDO Temperature Coefficient

—

Ta=-40°C~85°C�

LDOVS[1:0]=00B�

VIN=3.�V� ILOAD=100μA

—

0.48

�V/°C

∆VLINE_LDO LDO Line Regulation

— LDOVS[1:0]=00B�

2.6V≤VIN≤5.5V, ILOAD=100μA

—

0.3

%/V

VOUT_VCM

VCM Output Voltage

— VOREG=3.3V� No load

-5% 1.�5

+5%

TCVCM

VCM Temperature Coefficient

— Ta=-40°C~85°C� V

OREG

=3.3V�

ILOAD=10μA

—

0.�4

�V/°C

∆VLINE_VCM VCM Line Regulation

— 2.4V≤VOREG≤3.3V, No load

—

0.3

%/V

tVCMS

VCM Tu�n On Sta�le Ti�e

— VOREG=3.3V� No load

—

�s

IOH

Sou��e Cu��ent fo� VCM Output Pin — VOREG=3.3V, ∆VOUT_VCM=-�%

—

�A

IOL

Sink Cu��ent fo� VCM Output Pin

— VOREG=3.3V, ∆VOUT_VCM=+�%

—

�A

ADC & ADC Internal Reference Voltage (Delta Sigma ADC)

VOREG

Supply Voltage fo� VCM� ADC�

PGA

—

LDOEN=0

�.4

—

3.3

LDOEN=1

�.4

—

3.3

IADC

Additional Cu��ent fo� ADC

Ena�le

— VCM ena�le�

VRBUFP=1 and VRBUFN=1

—

�50

900

μA

— VCM ena�le�

VRBUFP=0 and VRBUFN=0

—

�00

�50

μA

— VCM disa�le�

VRBUFP=0 and VRBUFN=0

—

500

�50

μA

IADSTB

Stand�y Cu��ent

— MCU ente�s SLEEP �ode�

No load

—

μA

Resolution

—

�4

Bit

INL

Integ�al Non-linea�ity

— V

OREG

=3.3V� VREF=1.�5V�

∆SI=±450�V� PGA gain=1

—

±50

±�00

pp�

NFB

Noise F�ee Bits

— PGA gain=1�8�

Data �ate=1�.5Hz

—

15.4

—

Bit

ENOB

Effe�tive Nu��e� of Bits

— PGA gain=1�8

Data �ate=1�.5Hz

—

18.1

—

Bit

fADCK

ADC Clo�k F�equen�y

—

409.�

440

kHz

fADO

ADC Output Data Rate

— f

MCLK

=4.915�MHz�

FLMS[�:0]=000B

—

�40

— f

MCLK

=4.915�MHz�

FLMS[�:0]=010B

1�.5

—

1�00

VREFP

Exte�nal Refe�en�e Input Voltage

—

VREFS=1� VRBUFP=0�

VRBUFN=0

VREFN

+ 0.8

—

VOREG

VREFN

—

VREFP

- 0.8

VREF

— VREF=(VREFP–VREFN)×VGS

0.80

—

1.�5

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