VDP3108B datasheet(38/72 Pages) MICRONAS

38 / 72 page

VDP 31xxB

PRELIMINARY DATA SHEET

Micronas

Name

Default

Function

Mode

Number

of bits

I2C sub

address

OUTPUT PINS

h’10

w/r

output pin configuration

bit [2:0]

pin driver strength, MSY and CSY

7 = tristate

6 = minimum strength

0 = maximum strength

bit [4:3]

reserved (set to 0)

bit [5]

0/1

disable/enable internal resistor for

vertical and East/West drive output

bit [7:6]

function of CSY pin :

composite sync signal output

25 Hz output (field1/field2 signal)

no interlace (field 2), output = 0

1 MHz horizontal drive clock

PSTSY

VEWXR

CSYM

MISCELLANEOUS

h’32

w/r

fast blank interface mode

bit [0]

internal fast blank 1 from FBLIN1 pin

force internal fast blank 1 signal to high

bit [1]

0/1

internal fast blank active high/low

bit [2]

0/1

disable/enable clamping reference for

RGB outputs

bit [3]

full line MADC measurement window,

disables bit [3] in address h’25

bit [4]

0/1

horizontal flyback input active high/low

bit [6:5]

reserved (set to 0)

bit [7]

internal fast blank 1 from FBLIN1 pin

force internal fast blank 1 signal to low

FBMOD

FBFOH1

FBPOL

CLMPR

FLMW

FLPOL

FBFOL1

h’31

w/r

fast blank interface mode 2

bit [0]

internal fast blank 2 from FBLIN2 pin

force internal fast blank 2 signal to high

bit [1]

internal fast blank 2 from FBLIN2 pin

force internal fast blank 2 signal to low

bit [2]

fast blank input priority

FBLIN1 > FBLIN2

FBLIN1 < FBLIN2

bit [3]

fast blank monitor input select

monitor connected to FBLIN1 pin

monitor connected to FBLIN2 pin

bit [4]

half contrast switch enable

PORT0 enable / HCS disable

PORT0 disable / HCS enable

bit [5]

half contrast from HCS pin

force half contrast signal to high

bit [6]

0/1

half contrast active high/low at HCS pin

bit [7]

reserved (set to 0)

FBMOD2

FBFOH2

FBFOL2

FBPRIO

FBMON

HCSEN

HCSFOH

HCSPOL

h’34

w/r

IO Port

bit [6:0]

data to/from PORT[6:0]

bit [7]

front sync output at PORT1

PORT1 input/output enable

FSY output enable

bit [14:8]

port direction

switch PORT[bit–8] to input

switch PORT[bit–8] to output

bit [15]

port enable

COLOR[4:0] enable / PORT[6:2] disable

COLOR[4:0] disable / PORT[6:2] enable

IOPORT

IODATA

FSYOEN

IODIR

IOEN

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