VDP3108B datasheet(35/72 Pages) MICRONAS

35 / 72 page

VDP 31xxB

PRELIMINARY DATA SHEET

Micronas

Name

Default

Function

Mode

Number

of bits

I2C sub

address

h’4c

w v

digital OSD insertion contrast for R (amplitude range: 0 to 255)

bit [3:0]

0..13

R amplitude = CLUTn · (DRCT + 4)

14,15

invalid

picture frame insertion contrast for R (ampl. range: 0 to 255)

bit [7:4]

0..13

R amplitude = PFCR · (PFRCT + 4)

14,15

invalid

DRCT

PFRCT

h’48

w v

digital OSD insertion contrast for G (amplitude range: 0 to 255)

bit [3:0]

0..13

G amplitude = CLUTn · (DGCT + 4)

14,15

invalid

picture frame insertion contrast for G (ampl. range: 0 to 255)

bit [7:4]

0..13

G amplitude = PFCG · (PFGCT + 4)

14,15

invalid

DGCT

PFGCT

h’44

w v

digital OSD insertion contrast for B (amplitude range: 0 to 255)

bit [3:0]

0..13

B amplitude = CLUTn · (DBCT + 4)

14,15

invalid

picture frame insertion contrast for B (ampl. range: 0 to 255)

bit [7:4]

0..13

B amplitude = PFCB · (PFBCT + 4)

14,15

invalid

DBCT

PFBCT

PICTURE FRAME GENERATOR

h’4F

w v

bit [8:0] horizontal picture frame begin

code 0 = picture frame generator horizontally disabled

code 1FF = full frame

PFGHB

h’53

w v

bit [8:0] horizontal picture frame end

PFGHE

h’63

w v

bit [8:0] vertical picture frame begin

code 0 = picture frame generator vertically disabled

270

PFGVB

h’6f

w v

bit [8:0] vertical picture frame end

PFGVE

enable and priority – see under ‘PRIORITY BUS’

picture frame color – see under ‘COLOR LOOK-UP TABLE’

SCAN VELOCITY MODULATION

h’62

w v

video mode coefficients

bit [5:0]

gain1

bit [8:6]

differentiator delay 1 (0= filter off, 1...6= delay)

SVG1

SVD1

h’5e

w v

text mode coefficients

bit [5:0]

gain 2

bit [8:6]

differentiator delay 2 (0= filter off, 1...6= delay)

SVG2

SVD2

h’5a

w v

limiter

bit [6:0]

limit value

bit [8:5]

not used, set to ”0”

100

SVLIM

h’56

w v

delay and coring

bit [3:0]

adjustable delay, in 1/2 display clock steps,

(value 5 : delay of SVMOUT is the same as for

RGBOUT

bit [7:4]

coring value

bit [8]

not used, set to ”0”

SVDEL

SVCOR

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