VDP3108B datasheet(37/72 Pages) MICRONAS

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VDP 31xxB

PRELIMINARY DATA SHEET

Micronas

Name

Default

Function

Mode

Number

of bits

I2C sub

address

TIMING

h’67

w v

vertical blanking start

bit [8:0]

0..511

first line of vertical blanking

305

VBST

h’77

w v

vertical blanking stop

bit [8:0]

0..511

last line of vertical blanking

VBSO

h’73

w v

start of Black Level Expander measurement

bit [8:0]

0..511

first line of measurement, stop with first

line

of vertical blanking

AVST

h’5f

w v

bit [8:0] free running field period = (value

)4) lines

STIMP

HORIZONTAL DEFLECTION

h’7a

w v

adjustable delay of PLL2, clamping, and blanking (relative to

front sync)

adjust clamping pulse for analog RGB input

bit [8:0]

–256..+255

" 8 µs

–141

POFS2

h’76

w v

adjustable delay of flyback, main sync, csync and analog RGB

(relative to PLL2)

adjust horizontal drive or csync

bit [8:0]

–256..+255

"8 µs

POFS3

h’7e

w v

adjustable delay of main sync (relative to flyback)

adjust horizontal position for digital picture

bit [8:0]

20 steps

+1 µs

120

HPOS

h’5b

w/r

start of horizontal blanking

bit [8:0]

0..511

HBST

h’57

w/r

end of horizontal blanking

bit [8:0]

0..511

HBSO

h’6a

h’6e

h’72

w v

PLL2/3 filter coefficients, 1of5 bit code (n

+ set bit number)

bit [5:0]

proportional coefficient PLL3, 2–n–1

bit [5:0]

proportional coefficient PLL2, 2–n–1

bit [5:0]

integral coefficient PLL2, 2–n–5

PKP3

PKP2

PKI2

h’15

w/r

horizontal drive and vertical signal control register

bit [5:0]

0..63

horizontal drive pulse duration in

(internally limited to 4..61)

bit [6]

0/1

disable/enable horizontal PLL2 and PLL3

bit [7]

0/1

1: disable horizontal drive pulse during

flyback

bit [8]

0/1

reserved, set to ’0’

bit [9]

0/1

enable/disable ultra black blanking

bit [10]

0/1

0: all outputs blanked

1: normal mode

bit [11]

0/1

enable/disable clamping for analog RGB

input

bit [12]

0/1

disable/enable vertical free running mode

(FIELD is set to field2, no interlace)

bit [13]

0/1

enable/disable vertical protection

bit [14]

0/1

internal/external (under VPC control)

start of vertical and E/W signal

bit [15]

0/1

disable/enable phase shift of display clock

HDRV

EHPLL

EFLB

DUBL

EBL

DCRGB

SELFT

DVPR

XDEFL

DISKA

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