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BLUENRG-2 bảng dữ liệu(PDF) 118 Page - STMicroelectronics |
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BLUENRG-2 bảng dữ liệu(HTML) 118 Page - STMicroelectronics |
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118 / 190 page ![]() Functional details BlueNRG-2 118/190 DocID030675 Rev 2 Address offset Name RW Reset Description 0x30 MODE1 RW 0x00000110 Select mode for IO8 to IO15. 000b: GPIO mode. 001b: Serial1 mode. 100b: Serial0 mode. 101b: Serial2 mode. Refer to the detailed description below. 0x34 MODE2 RW 0x00000000 Select mode for IO16 to IO23. 000b: GPIO mode. 001b: Serial1 mode. 100b: Serial0 mode. 101b: Serial2 mode. Refer to the detailed description below. 0x38 MODE3 RW 0x00000000 Select mode for IO24 to IO25. 000b: GPIO mode. 001b: Serial1 mode. 100b: Serial0 mode. 101b: Serial2 mode. Refer to the detailed description below. 0x3C DATS RW 0x00000000 Set some bits of DATA when in GPIO mode without affecting the others (1 bit per IO). 0: no effect. 1: set at 1 the bit 0x40 DATC RW 0x00000000 Clear some bits of DATA when in GPIO mode without affecting the others (1 bit per IO) 0: no effect. 1: clear at 0 the bit 0x44 MFTX RW 0x00000000 Select the IO to be used as capture input for the MFTX timers. Refer to the detailed description below. Table 139: GPIO – DATA register description: address offset GPIO_BASE_ADDR+0x00 Bit Field name Reset RW Description 31:0 DATA 0x00000000 RW IO0 to IO25 data value. Writing to a bit will drive the written value on the corresponding IO when it is configured in GPIO mode and the output direction. Reading a bit indicates the pin value. Table 140: GPIO – OEN register description: address offset GPIO_BASE_ADDR+0x04 Bit Field name Reset RW Description 31:0 OEN 0x00000000 RW GPIO output enable register (1 bit per GPIO). 0: Input mode 1: Output mode |
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