DS31256 datasheet(176/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

176 of 183

14.

REVISION HISTORY

REVISION

DESCRIPTION

112102

New product release.

073103

Corrected various typographical errors, including:

Lifted some usage restrictions

Changed maximum number of T1 links from 64 to 60

Added U12 as a Ground in Table 3-A.

Removed PCI t5 and VIH exceptions to PCI 2.1 compliance.

Changed 8191 to 8188 in Figure 9-1 to be dword consistent.

Changed Logic 1 minimum from 2.2V to 1.8V in Section 13.

Added typical supply current and increase the maximum in Section 13.

Removed t5 compliance issue and added Note 16 in Section 13, PCI.

Added Chapter 15, Thermal Properties.

Updated recommended components in Section 17:Applications.

101104

Page 109: Removed “Chateau” from Figure 9-11.

Page 137, Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device

being used. The device ID was assigned by Dallas Semiconductor and is fixed at 31256h. The

device ID is 3134, not 31256.

Page 142, Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device

being used. The device ID was assigned by Dallas Semiconductor and is fixed at 31256h. The

device ID is 3134, not 31256.

Page 151: Section 11.1.2 Configuration Mode. Added info about how data cannot be passed

from the local bus to the PCI bus in this mode—The DS31256 PCI configuration registers

cannot be accessed via the PCI bus when the DS31256 is in Configuration mode (LMS=1). In

this mode no device registers are accessible via the PCI bus.

031405

Page 83: Added the last paragraph that states the DS31256 has no restrictions on the transmit

side, but lists the restrictions on the location and size of the receive buffers in host memory.

Page 90: Removed “Chateau” from Figure 9-2.

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