LPC47M182 datasheet(92/223 Pages) SMSC

92 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

Table 37 - Register Summary for an Individual UART Channel (continued)

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Enable

Receiver Line

Status

Interrupt

(ELSI)

Enable

MODEM

Status

Interrupt

(EMSI)

Interrupt ID

Bit

Interrupt ID

Bit (Note 5)

FIFOs

Enabled

(Note 5)

FIFOs

Enabled

(Note 5)

XMIT FIFO

Reset

DMA Mode

Select

(Note 6)

Reserved

RCVR Trigger

LSB

RCVR Trigger

MSB

Number of

Stop Bits

(STB)

Parity Enable

(PEN)

Even Parity

Select (EPS)

Stick Parity

Set Break

Divisor Latch

Access Bit

(DLAB)

OUT1

(Note 3)

OUT2

(Note 3)

Loop

Parity Error

(PE)

Framing Error

(FE)

Break

Interrupt (BI)

Transmitter

Holding

(THRE)

Transmitter

Empty

(TEMT)

(Note 2)

Error in RCVR

FIFO (Note 5)

Trailing Edge

Ring Indicator

(TERI)

Delta Data

Carrier Detect

(DDCD)

Clear to Send

(CTS)

Data Set

Ready (DSR)

Ring Indicator

(RI)

Data Carrier

Detect (DCD)

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Note 3: This bit no longer has a pin associated with it.

Note 4: When operating in the XT mode, this register is not available.

Note 5: These bits are always zero in the non-FIFO mode.

Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.

Note 7: The UART FCR’s is shadowed in the UART1 FIFO Control Shadow Register (Located at offset 0x1A in the in

the Power Control Logical Device, when LD_NUM=0, or Runtime Register Block Logical Device, when LD_NUM=1).

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