LPC47M182 datasheet(34/223 Pages) SMSC

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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

6.2

Host Processor Interface (LPC)

The host processor communicates with the LPC47M182 through a series of read/write registers via the

LPC interface. The port addresses for these registers are shown in Table 6.1. Register access is

accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.

6.3

LPC Interface

The following sub-sections specify the implementation of the LPC bus.

6.3.1

LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI

33MHz electrical signal characteristics.

SIGNAL

NAME

TYPE

DESCRIPTION

LAD[3:0]

I/O

LPC address/data bus. Multiplexed command, address and data bus.

nLFRAME

Input

Frame signal. Indicates start of new cycle and termination of broken cycle

nPCI_RESET

Input

PCI Reset. Used as LPC Interface Reset.

nLDRQ

Output

Encoded DMA/Bus Master request for the LPC interface.

nIO_PME

Power Mgt Event signal. Allows the LPC47M182 to request wakeup.

nLPCPD

Input

Powerdown Signal. Indicates that the LPC47M182 should prepare for power to be shut

on the LPC interface.

SER_IRQ

I/O

Serial IRQ.

PCI_CLK

Input

PCI Clock.

Note: The CLKRUN# signal is not implemented in this part.

6.3.2

LPC Cycles

The following cycle types are supported by the LPC protocol.

CYCLE TYPE

TRANSFER SIZE

I/O Write

1 Byte

I/O Read

1 Byte

DMA Write

1 Byte

DMA Read

1 Byte

LPC47M182 ignores cycles that it does not support.

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