LPC47M182 datasheet(88/223 Pages) SMSC

88 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

6.29.2 FIFO INTERRUPT MODE OPERATION

When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = “1”, IER bit 0 = “1”), RCVR

interrupts occur as follows:

A. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger

level; it is cleared as soon as the FIFO drops below its programmed trigger level.

B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is

cleared when the FIFO drops below the trigger level.

C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available

(IIR=04H) interrupt.

D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the

RCVR FIFO. It is reset when the FIFO is empty.

When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:

A. A FIFO timeout interrupt occurs if all the following conditions exist:

At least one character is in the FIFO.

The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop

bits are programmed, the second one is included in this time delay).

The most recent CPU read of the FIFO was longer than 4 continuous character times ago.

This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a

12 bit character.

B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay

proportional to the baudrate).

C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one

character from the RCVR FIFO.

D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received

or after the CPU reads the RCVR FIFO.

When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT

interrupts occur as follows:

A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as

soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT

FIFO while servicing this interrupt) or the IIR is read.

B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time

whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time

in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be

immediate, if it is enabled.

Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received

data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register

empty interrupt.

6.29.3 FIFO POLLED MODE OPERATION

With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of

operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the

polled mode of operation. In this mode, the user’s program will check RCVR and XMITTER status via the

LSR. LSR definitions for the FIFO Polled Mode are as follows:

Bit 0=1 as long as there is one byte in the RCVR FIFO.

LPC47M182 bảng dữ liệu(PDF) 88 Page - SMSC Corporation

LPC47M182 bảng dữ liệu(HTML) 88 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL