LPC47M182 datasheet(41/223 Pages) SMSC

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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC LPC47M182

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

DRIVE

SEL0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE

MOT

EN1

MOT

EN0

RESET

COND.

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and

unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and

unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a

hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic “1”.

BIT 7 RESERVED

Always read as a logic “1”

PS/2 Model 30 Mode

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported.

nDRV2

nDS1

nDS0

WDATA

F/F

RDATA

F/F

WGATE

F/F

nDS3

nDS2

RESET

COND.

N/A

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