LPC47M182 datasheet(79/223 Pages) SMSC

79 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC LPC47M182

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

6.28.3 TRANSMIT BUFFER REGISTER (TB)

Address Offset = 0H, DLAB = 0, WRITE ONLY

This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an

additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register

is loaded from the Transmit Buffer when the transmission of the previous byte is complete.

6.28.4 INTERRUPT ENABLE REGISTER (IER)

Address Offset = 1H, DLAB = 0, READ/WRITE

The lower four bits of this register control the enables of the five interrupt sources of the Serial Port

interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register.

Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled.

Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port

interrupt out of the LPC47M182. All other system functions operate in their normal manner, including the

Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described

below.

Bit 0

This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set

to logic “1”.

Bit 1

This bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”.

Bit 2

This bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the

interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the

source.

Bit 3

This bit enables the MODEM Status Interrupt when set to logic “1”. This is caused when one of the

Modem Status Register bits changes state.

Bits 4 through 7

These bits are always logic “0”.

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