MC68HC908AP16CFB datasheet(101/440 Pages) MOTOROLA

101 / 440 page

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

101

Data Sheet – MC68HC908AP Family

Section 8. Clock Generator Module (CGM)

8.1 Introduction

This section describes the clock generator module (CGM). The CGM

generates the base clock signal, CGMOUT, which is based on either the

oscillator clock divided by two or the divided phase-locked loop (PLL)

clock, CGMPCLK, divided by two. CGMOUT is the clock from which the

SIM derives the system clocks, including the bus clock, which is at a

frequency of CGMOUT÷2.

The PLL is a frequency generator designed for use with a low frequency

crystal (typically 32.768kHz) to generate a base frequency and dividing

to a maximum bus frequency of 8MHz.

8.2 Features

Features of the CGM include:

•

Phase-locked loop with output frequency in integer multiples of an

integer dividend of the crystal reference

•

Low-frequency crystal operation with low-power operation and

high-output frequency resolution

•

Programmable prescaler for power-of-two increases in frequency

•

Programmable hardware voltage-controlled oscillator (VCO) for

low-jitter operation

•

Automatic bandwidth control mode for low-jitter operation

•

Automatic frequency lock detector

•

CPU interrupt on entry or exit from locked condition

•

Configuration register bit to allow oscillator operation during stop

mode

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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