TMS320DM6431 datasheet(114/227 Pages) TI1

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System Interconnect

4.1 System Interconnect Block Diagram

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal

functions table.

On the DM6431 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system

peripherals are interconnected through a switch fabric architecture (see Figure 4-1). The switch fabric is

composed of multiple switched central resources (SCRs) and multiple bridges. The SCRs establish

low-latency connectivity between master peripherals and slave peripherals. Additionally, the SCRs provide

priority-based arbitration and facilitate concurrent data movement between master and slave peripherals.

Through an SCR, the DSP subsystem can send data to the DDR2 Memory Controller without affecting a

data transfer between the EMAC and L2 memory. Bridges are mainly used to perform bus-width

conversion as well as bus operating frequency conversion. For example, in Figure 4-1, Bridge 6 performs

a frequency conversion between a bus operating at DSP/3 clock rate and a bus operating at DSP/6 clock

rate. Furthermore, Bridge 5 performs a bus-width conversion between a 64-bit bus and a 32-bit bus.

The C64x+ Megamodule, the EDMA3 transfer controllers (EDMA3TC[2:0]), and the various system

peripherals can be classified into two categories: master peripherals and slave peripherals. Master

peripherals are typically capable of initiating read and write transfers in the system and do not rely on the

EDMA3 or on the CPU to perform transfers to and from them. The system master peripherals include the

C64x+ Megamodule, the EDMA3 transfer controllers, EMAC, and VPSS. Not all master peripherals may

connect to all slave peripherals. The supported connections are designated by "Y" in Table 4-1.

Table 4-1. System Connection Matrix

SLAVE PERIPHERALS/MODULES

MASTER

DDR2

SCR2, SCR6,

PERIPHERALS/MODULES

C64x+ SDMA

MEMORY

SCR4(1)

SCR7, SCR8(1)

CONTROLLER

C64x+ MDMA

–

VPSS

–

EMAC

EDMA3TC's (EDMA3TC2/TC1/TC0)

C64x+ CFG

–

(1)

All the peripherals/modules that support a connection to SCR2, SCR4, SCR6, SCR7, and SCR8 have access to all peripherals/modules

connected to those respective SCRs.

Figure 4-1 displays the DM6431 system interconnect block diagram. The following is a list that helps in

the interpretation of this diagram:

• The direction of the arrows indicates either a bus master or bus slave.

• The arrow originates at a bus master and terminates at a bus slave.

• The direction of the arrows does not indicate the direction of data flow. Data flow is typically

bi-directional for each of the documented bus paths.

• The pattern of each arrow's line indicates the clock rate at which it is operating— i.e., either DSP/3,

DSP/6, or MXI/CLKIN clock rate.

• A peripheral may have multiple instances shown in Figure 4-1 for the following reason:

–

The peripheral/module has master port(s) for data transfers, as well as slave port(s) for register

access, data access, and/or memory access. Examples of these peripherals are C64x+

Megamodule, EDMA3, VPSS, and EMAC.

System Interconnect

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