TMS320DM6431 datasheet(82/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

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Table 3-18. PINMUX0 Register Description

Bit

Field Name

Description

Pins Controlled

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

(default).

Sub-Block 0

CI[1:0] Function Select.

CI1(CCD9)/EM_A[19]/GP[45]

0 = No CCDC CI[1:0].

CI0(CCD8)/EM_A[20]/GP[44]

CI10SEL

Pins function as GPIO or EMIFA based on AEM and AEAW settings (default).

The combination of PINMUX0 fields AEM,

1 = Selects CCDC [1:0] (as CCD8 and CCD9, respectively) to get a 10-bit CCDC.

AEAW, and CI10SEL bits control the pin

To use the 10-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1.

muxing of these 2 pins. (1)

Reserved. For proper device operation, the user should only write "0" to this bit

29:25

RSV

(default).

Sub-Block 0

CCDC Field Select.

C_FIELD/EM_A[21]/GP[34]

0 = No CCDC Field (C_FIELD).

CFLDSEL

Pin functions as EMIFA EM_A[21] or GPIO based on AEM setting (default).

The combination of PINMUX0/1 fields

CFLDSEL and AEM control the muxing of this

1 = CCDC Field (C_FIELD).

pin. (1)

CCDC Write Enable Select.

Sub-Block 0

0 = No CCDC Write Enable.

Pin functions as EMIFA EM_R/W or GPIO based on AEM setting (default).

C_WE/EM_R/W/GP[35]

CWENSEL

1 = CCDC Write Enable (C_WE).

The combination of PINMUX0 fields CWENSEL

Pin functions as CCDC Write Enable C_WE.

and AEM control the muxing of this pin. (1)

Applicable only for AEM = 0 (000b) or 5 (101b).

Sub-Block 0

CCDC HD and VD Select.

VD/GP[53]

0 = No CCDC HD and VD.

HVDSEL

HD/GP[52]

Pins function as GPIO (GP[53] and GP[52]) (default).

The PINMUX0 field HVDSEL alone controls the

1 = CCDC HD and VD.

muxing of these 2 pins.

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

(default).

Sub-Block 0

PCLK/GP[54]

YI7(CCD7)/GP[43]

CCDC Select.

YI6(CCD6)/GP[42]

This bit field determines if CCDC is supported or not.

YI5(CCD5)/GP[41]

0 = CCDC not supported.

YI4(CCD4)/GP[40]

CCDCSEL

Pins function as GPIO (GP[54] and GP[43:36]) (default).

YI3(CCD3)/GP[39]

YI2(CCD2)/GP[38]

1 = CCDC supported.

YI1(CCD1)/GP[37]

Pins function as CCDC PCLK, YI[7:0].

YI0(CCD0)/GP[36]

The PINMUX0 field CCDCSEL alone controls

the muxing of these 9 pins.

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

(default).

(1)

For the full set of valid configurations of these pins, see Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary.

Device Configurations

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