TMS320DM6431 datasheet(28/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

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Table 2-9. EMIFA Terminal Functions (Boot Configuration)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

EMIFA: BOOT CONFIGURATION

EM_A[4]/GP[10]/

IPD

These pins are multiplexed between the EMIFA and GPIO. When

A17

B21

I/O/Z

(AEAW2/PLLMS2)

DVDD33

RESET or POR is asserted, these pins function as EMIFA

configuration pins. At reset if AEM[2:0] = 001 (EMIFA in 8-bit Async

EM_A[1]/(ALE)/GP[

IPD

mode), then the input states of AEAW[2:0] are sampled to set the

9]/

A16

B20

I/O/Z

DVDD33

EMIFA Address Bus Width. After reset, these pins function as EMIFA

(AEAW1/PLLMS1)

or GPIO pin functions based on pin mux selection.

EM_A[2]/(CLE)/GP

For more details on the AEAW/PLLMS functions, see Section 3.5.1.2,

IPD

[8]/

B16

A20

I/O/Z

EMIFA Address Bus Width (AEAW) and Fast Boot PLL Multiplier

DVDD33

(AEAW0/PLLMS0)

Select (PLLMS).

EM_BA[1]/

IPD

These pins are multiplexed between the EMIFA and GPIO. When

C16

C20

I/O/Z

GP[5]/(AEM0)

DVDD33

RESET or POR is asserted, these pins function as EMIFA

configuration pins. At reset, the input states of AEM[2:0] are sampled

EM_BA[0]/

IPD

C17

E20

I/O/Z

to set the EMIFA Pinout Mode.

GP[6]/(AEM1)

DVDD33

For more details, see Section 3.5.1, Configurations at Reset. After

reset, these pins function as EMIFA or GPIO pin functions based on

EM_A[0]/

IPD

pin mux selection.

B17

C21

I/O/Z

GP[7]/(AEM2)

DVDD33

For more details on the AEM functions, see Section 3.5.1.1, EMIFA

Pinout Mode (AEM[2:0]).

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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