TMS320DM6431 datasheet(112/227 Pages) TI1

112 / 227 page

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

For details on C64x+ Megamodule configuration, see the TMS320C64x+ DSP Megamodule

Reference Guide (literature number SPRU871).

Special considerations: Bootloader disables C64x+ cache—For all boot modes that default to

DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,

BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2,

L1P, and L1D) so that upon exit from the bootloader code, all C64x+ memories are configured

as all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and L1DCFG.L1DMODE = 0h).

If cache use is required, the application code must explicitly enable the cache. For more

information on boot modes, see Section 3.4.1, Boot Modes. For more information on the

bootloader, see the Using the TMS320DM643x Bootloader Application Report (literature

number SPRAAG0).

Peripherals configuration: see the respective peripheral user’s guide.

Special considerations: DDR2 memory controller—the Peripheral Bus Burst Priority Register

(PBBPR) should be programmed to ensure good DDR2 throughput and to prevent command

starvation (prevention of certain commands from being processed by the DDR2 memory

controller). For more details, see the TMS320DM643x DMP DDR2 Memory Controller User’s

Guide (literature number SPRU986). A hex value of 0x20 is recommended for the PBBPR

PR_OLD_COUNT field to provide a good DSP performance and still allow good utilization by

other modules.

112

Device Configurations

Submit Documentation Feedback

TMS320DM6431 bảng dữ liệu(PDF) 112 Page - Texas Instruments