WM8232 datasheet(31/141 Pages) CIRRUS

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WM8232

Rev 4.6

LVDS SYNCHRONOUS OUTPUT

The LVDS synchronous output function can be used in LVDS 16-bit 5pair mode, 10-bit 3pair mode

and 12-bit 4 pair mode. In these LVDS output mode, the output data packet cycle is not same as

MCLK clock period, so that the output data at pixel counter = 0 will not be same format when the line

length is odd number.

If OUTSYNC = 1, the LVDS output format will be synchronized to pixel counter = 0.

When the line length is even number, the output data at pixel counter = 0 will be always same format,

so that the OUTSYNC is invalid. Also, the OUTSYNC is invalid in other LVDS and CMOS format. The

following shows detailed information of this mode.

Odd number line length

In odd number line length operation, the output data at pixel counter = 0 will not be same format as

shown in Figure 17. When set the OUTSYNC register, the LVDS output format will be synchronized to

pixel counter = 0 as shown in Figure 18 below.

Last pixel

Pix counter

LVDS

data output

Odd number line length, OUTSYNC = 0

Line 0

Line 1

Line 2

Figure 17 LVDS output data cycle (odd number line length, OUTSYNC=0)

Last pixel

Pix counter

LVDS

data output

Odd number line length, OUTSYNC = 1

Line 0

Line 1

Line 2

Figure 18 LVDS output data cycle (odd number line length, OUTSYNC=1)

Even number line length

When the line length is even number, the output data at pixel counter = 0 will be always same format,

so that the OUTSYNC is invalid.

Last pixel

Pix counter

LVDS

data output

Line 0

Even number line length (OUTSYNC is invalid)

Line 1

Line 2

Figure 19 LVDS output data cycle (even number line length)

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