WM8232 datasheet(55/141 Pages) CIRRUS

55 / 141 page

WM8232

Rev 4.6

BLC configuration

BLC start pixel

configuration

0xBD,0xBE OB_START

BLC period

configuration

0x53,0x54 BPIX_AVAIL

Coarse adjust

configuration

0x51[2:0] CADUR

0x51[3] CA_EVERYLINE

Fine adjust

configuration

0x51[4] FA_EN

0x51[6] FA_EVERYLINE

BLC target level

configuration

0x4A0x4D,0x50

TARGETINn*

Set the frame start

indicator (*2)

0x52[0] FRAME_START

Start the frame

sequence

TGSYNC

Line length

configuration

enabled

0xA1,0xA2 LLENGTH

0xA0[0] TG_EN

TG mode

selection

Master mode

0xA0[1] TGMD=1

Slave mode

0xA0[1] TGMD=0

TG enabled (*1)

Figure 45 BLC Configuration

Notes:

1. This must be set when BLC is used.

2. With this register set, frame sequence will be started after TGSYNC is recognized. Therefore this

should be set within the last line of previous frame.

PGA CONFIGURATION

The WM8232 provides an Automatic Gain Control (AGC) function. The output code is calibrated to

target level by this automatic gain control function. See

“Automatic Gain Control (AGC)” section for

details of AGC sequence. Also, see the following instruction to configure AGC related registers. The

analogue PGA (APGA) and digital PGA (DPGA) can be configured manually when AGC is not

required. See

“Offset Adjust and Programmable Gain” section for details of PGA configuration.

PGA configuration

APGA

configuration

AGC

configuration

0x2F,0x32,0x35

AGAININ*

Using AGC function

Yes

DPGA

configuration

0x3A,3B,40,41,46,47

DGAININ*

Manual PGA configuration

Figure 46 PGA Configuration

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