WM8232 datasheet(54/141 Pages) CIRRUS

54 / 141 page

WM8232

Rev 4.6

VRLC CONFIGURATION

VRLC configuration is the setting for VRLC voltage, which is used for input signal clamp voltage at line

clamp operation. The VRLC voltage is also used as the reference level of non-CDS (S/H) operation.

See

“Reset Level Clamping (RLC)” section and “CDS/Non-CDS Processing” section for details of

configuring this register.

0x06[4:0] VRLC_VSEL

VRLC output voltage

configuration

0x04[7] VRLC_TOP_SEL

VRLC output range

configuration

VRLC configuration

0x06[7]

VRLCEN=0

VRLC disabled

(External VRLC operation)

VRLC

configuration

0x06[7]

VRLCEN=1

Figure 43 VRLC Configuration

OFFSET DAC CONFIGURATION

The offset DAC is used for black level offset compensation. WM8232 has BLC function to calibrate

black level. In this mode, the offset DAC will be configured automatically. When this function is not

needed, the offset DAC can be configured manually. See

“Overall Signal Flow Summary” section for

details of offset DAC configuration, and see

“BLC Scenarios of Operation” for details of BLC sequence.

Offset DAC configuration

Offset DAC

configuration

BLC

configuration

0x24~0x2C DACIN*

Using BLC function

Yes

Figure 44 Offset DAC Configuration

BLC Configuration

TG enabled: This must be enabled when AGC function is used.

BLC start pixel configuration: This is start pixel configuration for BLC.

BLC period configuration: BLC will operate while this period from BLC start pixel.

BLC target level configuration: This is configuration for the target level of black pixel.

Coarse adjust configuration:

CADUR: This is the coarse adjust iteration setting during BLC period.

CA_EVERYLINE: When this register set, coarse adjust will operate on every line.

Fine adjust configuration: This is configuration for Coarse adjust iteration.

FA_EN: When this register set, fine adjust will operate during BLC period.

FA_EVERYLINE: When this register set, fine adjust will operate on every line.

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