WM8232 datasheet(48/141 Pages) CIRRUS

48 / 141 page

WM8232

Rev 4.6

LINE-BY-LINE OPERATION

Certain linear sensors give colour output on a line-by-line basis. i.e. a full line of red pixels followed by

a line of green pixels followed by a line of blue pixels.

The WM8232 can accommodate this type of input by setting the LINEBYLINE register bit high. The

offset and gain values that are applied to every input channel can be selected, by internal

multiplexers, to come from IN1, IN2 or IN3 offset and gain registers. This allows the gain and offset

values for each of the input colours to be setup individually at the start of a scan.

When register bit ACYC=0 the gain and offset multiplexers are controlled via the INTM[1:0] register

bits. When INTM=00 the IN1 offset and gain control registers are used to control every input channel,

INTM=01 selects the IN2 offset and gain registers and INTM=10 selects the IN3 offset and gain

registers to control every input channel.

When register bit ACYC=1, ‘auto-cycling’ is enabled, and the input channel switches to the next offset

and gain registers in the sequence by TGSYNC. The sequence is IN1  IN2  IN3  IN1

… offset

and gain registers applied to every input channel.

AGAININ1,

DGAININ1,

DACIN1

AGAININ2,

DGAININ2,

DACIN2

AGAININ2,

DGAININ2,

DACIN2

TGSYNC

LINEBYLINE 0x23[0]

IN1

LINEBYLINE

INTM Mode

AGAININ1, DGAININ1, DACIN1

AGAININ2, DGAININ2, DACIN2

AGAININ3, DGAININ3, DACIN3

IN2

IN3

Normal Operation

INTM 0x23[3:2]

AGAININ1, DGAININ1, DACIN1

AGAININ2, DGAININ2, DACIN2

AGAININ3, DGAININ3, DACIN3

INTM=00

INTM=01

INTM=10

Reserved

INTM=11

AGAININ3,

DGAININ3,

DACIN3

ACYC 0x23[1]

INTM Mode (depends on INTM register)

Auto Cycling mode (IN1 -> IN2 -> IN3)

ACYC=0

ACYC=1

AGAININ1, DGAININ1, DACIN1

AGAININ2, DGAININ2, DACIN2

AGAININ3, DGAININ3, DACIN3

Must be set to 0

Figure 33 Line-by-Line Operation (ACYC=0, INTM mode)

AGAININ3,

DGAININ3,

DACIN3

AGAININ2,

DGAININ2,

DACIN2

AGAININ1,

DGAININ1,

DACIN1

AGAININ3,

DGAININ3,

DACIN3

AGAININ1,

DGAININ1,

DACIN1

AGAININ2,

DGAININ2,

DACIN2

TGSYNC

LINEBYLINE 0x23[0]

IN1

LINEBYLINE

Auto Cycling Mode

AGAININ1, DGAININ1, DACIN1

AGAININ2, DGAININ2, DACIN2

AGAININ3, DGAININ3, DACIN3

AGAININ3,

DGAININ3,

DACIN3

AG1,

DG1,

DA1

AGAININ2,

DGAININ2,

DACIN2

AG1,

DG1,

DA1

IN2

IN3

Normal Operation

ACYC 0x23[1]

INTM Mode (depends on INTM register)

Auto Cycling mode (IN1 -> IN2 -> IN3)

ACYC=0

ACYC=1

AGAININ1, DGAININ1, DACIN1

AGAININ2, DGAININ2, DACIN2

AGAININ3, DGAININ3, DACIN3

Figure 34 Line-by-Line Operation (ACYC=1, Auto-cycling mode)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R35 (23h)

Cycle mode

control

3:2

INTM[1:0]

When LINEBYLINE=1,

controls the GAIN and DAC mux selector when ACYC=0

00 = IN1

01 = IN2

10 = IN3

11 = reserved

ACYC

when LINEBYLINE=1, determines the function of the MUX control

0 = decided by INTM register

1= auto-cycling enabled

LINEBYLINE

select line by line operation

0=normal operation

1=Line by Line operation

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