STM32F328C8 datasheet(95/109 Pages) STMICROELECTRONICS

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STM32F328C8

Electrical characteristics

100

Figure 26. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

loads directly without the use of an external operational amplifier. The buffer can be bypassed by

configuring the BOFFx bit in the DAC_CR register.

tSETTLING(3

)

Settling time (full scale: for

a 12-bit input code

transition between the

lowest and the highest input

codes when DAC_OUT

reaches final value ±1LSB

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

-3

µs

Update

rate(3)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to

i+1LSB)

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

MS/

tWAKEUP(3)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

-6.5

µs

PSRR+ (1)

Power supply rejection ratio

(to VDDA) (static DC

measurement

No RLOAD, CLOAD = 50 pF

–67

–40

1. Guaranteed by design, not tested in production.

2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is

involved.

3. Data based on characterization results, not tested in production.

Table 61. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

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