SPC564A80L7 datasheet(150/157 Pages) STMICROELECTRONICS

150 / 157 page

Document revision history

SPC564A74L7, SPC564A80B4, SPC564A80L7

150/157

Doc ID 15399 Rev 9

02-Apr-2010

(cont)

Signal Details table updated:

– Added eTPU2 reaction channels

– Changed IRQ[0:15] to two ranges, excluding IRQ6, which does not exist on this

device

– Changed TCR_A to TCRCLKA (TCR_A is the pin name, not the signal name)

– Changed WE_BE[0:1] to WE_BE[0:3] (2 new signals added to Rev. 2). Also

changed notation from “WE_BE[n]” to “WE[n]/BE[n]” to be consistent.

Changes to Power/ground segmentation table:

– ADDR[20:21] removed from VDDE2 segment; they are in VDDE-EH

– CAL_CS1 removed from VDDE12 segment (there is no CAL_CS1 on this device)

– CAL_EVTO and CAL_MCKO removed from VDDE12 segment. Those pins do not

exist

– VDDE-VDDEH renamed to VDDE-EH

– EMIOS24 removed from VDDEH segment. That pin does not exist.

– ETPUA[0:9] added to VDDEH4 segment

– Renamed TCR_A in VDDEH4 segment to TCRCLKA.

– EXTAL and XTAL added to VDDEH6 segment

– AN15-FCK added to VDDEH7 segment

– GPIO98, GPIO99, GPIO206, GPIO207 and GPIO219 added to VDDEH7 segment.

– MSEO1 added to VDDEH7 segment

– Power segment VDDEH1A renamed to VDDEH1

Changes to 176-pin package pinout:

– Changed pin 9 from AN38 to AN8.

– Added note that pin 96 (VSS) should be tied low.

Changes to 208-ball package ballmap:

– Changed ball B3 from AN38 to AN8.

– Added note that ball N13 (VSS) should be tied low.

324-ball package ballmap updated for Rev. 2 silicon

– Renamed VDDA (A6) to VDDA0

– Renamed VSSA (A7) to VSSA0

– AN8 was on ball C5; it is now on D6

– AN38 was on ball D6; it is now on C5

– Renamed VSSA (A15) to VSSA1

– Renamed VDDA (C15) to VDDA1

– Rename VSSA (B15) to VSSA1

BGA288 package is no longer offered

Changes to features list:

– Correction: there are 6 reaction channels (was noted as 5)

– Development Trigger Semaphore (DTS) added to features list and feature details

– FlexRay module now has 128 message buffers (was 64) and ECC support

Added note after JTAG pin AC electrical characteristics table detailing JTAG EVTI and

RDY signal clocking with TCK. This affects debuggers.

Table 56.

Revision history (continued)

Date

Revision

Changes

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