STV2050A datasheet(34/83 Pages) STMICROELECTRONICS

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STV2050A - VIDEO PATTERN GENERATOR

The FBLK output is switched to ´high´ voltage when at least one color is activated by the COV

bits in the EA register when the STA bit in the D7 register is activated. If no color is selected,

the FBLK output is switched to ´low´ voltage. For other features of the FBLK pin, refer to Sec-

tion 8.4 "FAST BLANKING" on page 43.

The video signal representing a vertical line (grid, border, cursor) has the shape of a pulse with

a width of one system clock cycle.

7.1.2 Pattern Visibility Adjustment

Since the bandwidth of the RGB signal path is limited, horizontal and vertical lines may appear

on the screen with different brightness levels. To compensate for this effect, it is possible to

adjust the brightness values for the horizontal line (PBH[3:0]) bits and the vertical line

(PBV[3:0]) bits in the D6 register of the video pattern.

The video brightness has 4-bit resolution. The 0(hex) value corresponds to the 0.0 V output

from the video DACs. The 1(hex) value corresponds to a typical 0.6 V output. All other steps

are equidistant.

Figure 16. Pattern Visibility Adjustment

If the PBH bit is set to zero, the amplitude of the auto-alignment pattern is determined by the

PBV bit.

Using the VDC bit in the EA register, the frequency compensation of the video DACs can be

adapted according to the system clock.

PAS[1]

0: Grid Off

1: Grid On

PAS[0]

0: Border Off

1: Border On

VDC

0: Low Current

1: High Current

0.6 V

2.3 V

0000 0001 0010

1111

Analog

output

Digital

value

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