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STV2050A bảng dữ liệu(PDF) 22 Page - STMicroelectronics

tên linh kiện STV2050A
Giải thích chi tiết về linh kiện  AUTOMATIC MULTISCAN DIGITAL CONVERGENCE PROCESSOR
PDF  83 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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STV2050A bảng dữ liệu(HTML) 22 Page - STMicroelectronics

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STV2050A - TIMEBASES
5 TIMEBASES
5.1 LINE LOCKED PLL AND SYSTEM CLOCK
A frequency-multiplying PLL derives the internal
system clock from the incoming signal at the
SYNH pin. This signal is derived from horizontal deflection.
Figure 9. Line-Locked PLL and System Clock
The PLL is designed to drive 1H, 2H, HDTV and SVGA applications. Two loop filters can be
implemented using the FILT (pin 24) and FLT2 (pin 25) pads. The selection can be forced by
the PRS bit in the D5 register.
The horizontal deflection is often turned off when switching TV set modes. Therefore the PLL
provides a base frequency when the external sync signal is missing (both H and V sync sig-
nals are missing).
PRS
0 = FILT selected (2H and above range operation recommended)
1 = FLT2 selected (1H range operation recommended)
PLL
15 K
10 nF
15 K
10 nF
100 nF
1.5 nF
SYNH
PRS
STV2050A
System
Clock



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