STV2050A datasheet(23/83 Pages) STMICROELECTRONICS

23 / 83 page

23/83

STV2050A - TIMEBASES

The N(clk/line) ratio between the system clock and the incoming sync signal is calculated using

the HGD[5:0] and HRD[5:0] values in the D8 register. (Refer to Section 7.2.1 "Horizontal Grid

Adjustment" on page 35):

N(clk/line) = 14 ∗ (HGD+1) + 2 ∗ (HRD+1)

where:

N(clk/line) < 512

HGD

HRD

For all modes, in normal operation, the incoming timing signal at the SYNH pin will not have a

phase deviation greater than

± 2 µs from line to line. Greater phase deviations may occur

when switching modes or changing channels. The PLL is expected to recover from these

events and lock within one vertical field of consistent phase that is within the normal horizontal

operation limits.

5.2 SYNCHRONIZATION INPUTS

The two synchronization inputs, SYNH (pin 27) and SYNV (pin 28) slice the Line or the Frame

Flyback, respectively, via a Schmitt trigger.

This also ensures a very stable detection of the synchronization signals, regardless of the

temperature.

Figure 10. Synchronisation Signals

5.3 HORIZONTAL TIMEBASE

The horizontal timing is based on the built-in PLL.

5.3.1 Horizontal DAC Phase

In order to compensate the delay of the external amplifiers and the response time of the con-

vergence coils (td), the values for convergence correction are given out prior to the corre-

sponding horizontal video position. The time delay between video position and the output of

Logic

Level

(1)

(2)

down

STV2050A bảng dữ liệu(PDF) 23 Page - STMicroelectronics