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STV2050A bảng dữ liệu(PDF) 17 Page - STMicroelectronics

tên linh kiện STV2050A
Giải thích chi tiết về linh kiện  AUTOMATIC MULTISCAN DIGITAL CONVERGENCE PROCESSOR
PDF  83 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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STV2050A bảng dữ liệu(HTML) 17 Page - STMicroelectronics

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STV2050A - SLAVE I²C BUS INTERFACE
3.4 READ COMMANDS
Read commands may access the IC internal RAM as well as all I²C registers. Read com-
mands in the 00 to CF range read from the RAM bank that is defined by the two CBS bits that
have been previously transmitted to the E7 register by a write command.
Addresses in the D0 to E2 range are mapped to the corresponding section of the red color
RAM if the RRP bit in the EF register is ‘0’. Otherwise the corresponding internal register
values are transmitted.
If the SA is in the 00 to CF address range, the position of the cursor is implicitly defined by the
SA. An access to any other SAs will switch off the cursor. It will be switched on again if an ad-
dress in the 00 to CF range is selected.
Three formats of read commands are supported:
– Random read commands from any valid IC internal address
S DW SA S DR SA D0 D1 D2 P
If the auto-increment function is enabled, the internal address is at the SA+1 after the com-
mand, otherwise it is still at the SA.
– Read commands from the actual internal address
S DR SA D0 D1 D2 P
If the auto-increment function is enabled, the internal address is at the SA+1 after the com-
mand, otherwise it is still at the SA.
– Auto-increment read commands from addresses within the 00 to CF address range
with random start address.
S DW SA S DR SA D0 D1 D2...... Dn P
If the auto-increment function is enabled, the internal address counter is incremented after 3
bytes are read, otherwise the SA is always read and the internal address does not change.
When the last byte of the CF address has been transmitted, the IC internal auto-increment ad-
dress counter stops counting and the CF value will be read out again.
3.5 I²C I/O LINES
Digital filters suppress pulses that are less than 1 or 2 clock pulses at the SDAI and SCLS in-
puts.



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