M16CSLASH62P datasheet(69/349 Pages) MITSUBISHI

69 / 349 page

Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Generation Circuit

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Figure 1.9.10. State Transition to Stop Mode and Wait Mode

Reset

Medium-speed mode

(divided-by-8 mode)

High-speed, medium-

speed mode

Stop mode

Wait mode

Interrupt

CM10=1

Interrupt

Normal mode

Low-speed, low power

dissipation mode

CM10=1

Stop mode

Interrupt

Wait mode

Interrupt

CM10=1

Stop mode

All oscillators stopped

Interrupt

Wait mode

WAIT

instruction

(Note 3)

Interrupt

CPU operation stopped

When

low-

speed

mode

When

low power

dissipation

mode

PLL operation

mode

Notes 1, 2

Note 1: Do not go directly from PLL operation mode to wait or stop mode.

Note 2: PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.

Note 3: When the PM21 bit = 0 (system clock protective function unused).

Note 4: The ring oscillator clock divided by 8 provides the CPU clock.

Note 5: Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21=0 (ring oscillator turned off).

Ring oscillator, Ring oscillator

dissipation mode

Wait mode

Interrupt

CM10=1

Interrupt

(Note 4)

Stop mode

WAIT

instruction

(Note 3)

WAIT

instruction

(Note 3)

WAIT

instruction

(Note 3)

CM07=0

CM06=1

CM05=0

CM11=0

CM10=1

(Note 5)

Figure 1.9.10 shows the state transition from normal operation mode to stop mode and wait mode. Figure

1.9.11 shows the state transition in normal operation mode.

Table 1.9.7 shows a state transition matrix describing allowed transition and setting. The vertical line

shows current state and horizontal line shows state after transition.

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