M16CSLASH62P datasheet(38/349 Pages) MITSUBISHI

38 / 349 page

Bus

Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

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Figure 1.7.4. Example in which Wait State was Inserted into Read Cycle by RDY Signal

BCLK

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

BCLK

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

In an instance of separate bus

In an instance of multiplexed bus

Accept timing of RDY signal

: Wait using RDY signal

: Wait using software

Accept timing of RDY signal

Shown above is the case where CSEiW to CSEi1W (i = 0 to 3) bits are “002” (one wait state).

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(6) The RDY Signal

This signal is provided for accessing external devices which need to be accessed at low speed. If input on

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the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in

________

the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY

signal was acknowledged.

______

______ ________

________

______

________

__________

A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA

________

Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle

is executed. Figure 1.7.4 shows example in which the wait state was inserted into the read cycle by the

________

RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register

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to “0” (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.

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