M16CSLASH62P datasheet(39/349 Pages) MITSUBISHI

39 / 349 page

Bus

Mitsubishi microcomputers

M16C / 62P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev.1.0

Specifications in this manual are tentative and subject to change.

Table 1.7.4. Microcomputer Status in Hold State

Item

Status

BCLK

Output

_______

_____

________

_________ _______ _______

A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE

High-impedance

I/O ports

P0, P1, P3, P4(Note 2)

High-impedance

P6 to P14(Note 1)

Maintains status when hold signal is received

__________

HLDA

Output “L”

Internal peripheral circuits

ON (but watchdog timer stops)

ALE signal

Undefined

__________

HOLD > DMAC > CPU

(7) Hold Signal

This signal is used to transfer control of the bus from the CPU or DMA to an external circuit. When input

__________

on the HOLD pin is asserted “L”, the microcomputer goes to a hold state after completing the bus access

__________

then in progress. While the HOLD pin is held “L”, the microcomputer remains in a hold state, outputting a

__________

low signal from the HLDA pin.

Table 1.7.4 shows the microcomputer status in the hold state.

__________

Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.

Figure 1.7.5. Bus-using Priorities

Note 1: P11 to P14 are included in the 128-pin version.

Note 2: When I/O port function is selected.

(8) BCLK Output

If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that

of the CPU clock is output as BCLK from the BCLK pin. Refer to “CPU clock and pheripheral clock”.

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