LAN9250 datasheet(200/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 200

 2015 Microchip Technology Inc.

11.15.6

HOST MAC MII ACCESS REGISTER (HMAC_MII_ACC)

This read/write register is used in conjunction with the Host MAC MII Data Register (HMAC_MII_DATA) to access the

internal PHY registers. Refer to Section 12.2.18, "PHY Registers" for a list of accessible PHY registers and PHY address

information.

Offset:

06h

Size:

32 bits

Bits

Description

Type

Default

31:16

RESERVED

15:11

PHY Address (PHY_ADDR)

This field must be loaded with the PHY address that the MII access is

intended for. Refer to Section 12.1.1, "PHY Addressing," on page 210 for

additional information on PHY addressing.

R/W

00000b

10:6

MII Register Index (MIIRINDA)

These bits select the desired MII register in the PHY.

R/W

00000b

5:2

RESERVED

MII Write (MIIWnR)

Setting this bit tells the PHY that this will be a write operation using the Host

MAC MII Data Register (HMAC_MII_DATA). If this bit is cleared, a read oper-

ation will occur, packing the data in the Host MAC MII Data Register

(HMAC_MII_DATA).

R/W

MII Busy (MIIBZY)

This bit must be polled to determine when the MII register access is com-

plete. This bit must read a logical 0 before writing to this register or the Host

MAC MII Data Register (HMAC_MII_DATA).

The LAN driver software must set this bit in order for the device to read or

write any of the MII PHY registers.

During a MII register access, this bit will be set, signifying a read or write

access is in progress. The MII data register must be kept valid until the Host

MAC clears this bit during a PHY write operation. The MII data register is

invalid until the Host MAC has cleared this bit during a PHY read operation.

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