LAN9250 datasheet(43/421 Pages) MICROCHIP

tên linh kiện	LAN9250

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 2015 Microchip Technology Inc.

DS00001913A-page 43

LAN9250

PHY Reset (PHY_RST)

Setting this bit resets the PHY. The internal logic automatically holds the PHY

reset for a minimum of 102uS. When the PHY is released from reset, this bit

is automatically cleared. All writes to this bit are ignored while this bit is set.

Note:

This bit is not accessible via the EEPROM Loader’s register

initialization function (Section 13.4.5).

R/W

Digital Reset (DIGITAL_RST)

Setting this bit resets the complete chip except the PLL and PHY. All system

CSRs are reset except for any NASR type bits. Any in progress EEPROM

commands (including RELOAD) are terminated.

The EEPROM Loader will automatically reload the configuration following

this reset, but will not reset the PHY. If desired, the above PHY reset can be

issued once the device is configured.

When the chip is released from reset, this bit is automatically cleared. All

writes to this bit are ignored while this bit is set.

Note:

This bit is not accessible via the EEPROM Loader’s register

initialization function (Section 13.4.5).

R/W

Bits

Description

Type

Default

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