LAN9250 datasheet(94/421 Pages) MICROCHIP

94 / 421 page

LAN9250

DS00001913A-page 94

 2015 Microchip Technology Inc.

9.5

Indexed Address Mode

In Indexed Address mode, access to the internal registers and memory of the device are indirectly mapped using Index

and Data registers. The desired internal address is written into the device at a particular offset. The value written is then

used as the internal address when the associate Data register address is accessed. Three Index / Data register sets

are provided allowing for multi-threaded operation without the concern of one thread corrupting the Index set by another

thread. Endianness can be configured per Index / Data pair. Another Data register is provided for access to the FIFOs.

The host address register map is given below. In 8-bit data mode, the host address input (ADDR[4:0]) is a BYTE

address. In 16-bit data mode, ADDR0 is not provided and the host address input (ADDR[4:1]) is a WORD address.

As discussed below in Section 9.5.5.2, "Index Register Bypass FIFO Access", the TX and RX Data FIFOs are accessed

when reading or writing at address 18h-1Bh.

As discussed below in Section 9.5.5.3, "FIFO Direct Select Access", when the FIFOSEL input is active, all access is to

or from the TX and RX Data FIFOs.

TABLE 9-3:

HOST BUS INTERFACE INDEXED ADDRESS MODE REGISTER MAP

FIFOSEL

BYTE

ADDRESS

SYMBOL

00h-03h

HBI_IDX_0

Host Bus Interface Index Register 0

04h-07h

HBI_DATA_0

Host Bus Interface Data Register 0

08h-0Bh

HBI_IDX_1

Host Bus Interface Index Register 1

0Ch-0Fh

HBI_DATA_1

Host Bus Interface Data Register 1

10h-13h

HBI_IDX_2

Host Bus Interface Index Register 2

14h-17h

HBI_DATA_2

Host Bus Interface Data Register 2

18h-1Bh

TX_DATA_FIFO

RX_DATA_FIFO

TX Data FIFO

RX Data FIFO

1Ch-1Fh

HBI_CFG

Host Bus Interface Configuration Register

1na

TX_DATA_FIFO

RX_DATA_FIFO

TX Data FIFO

RX Data FIFO

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