LAN9250 datasheet(36/421 Pages) MICROCHIP

36 / 421 page

LAN9250

DS00001913A-page 36

 2015 Microchip Technology Inc.

(45ns). For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal

to, or greater than the time specified in the table. Dummy reads of the BYTE_TEST register are not required as long as

the minimum time period is met.

Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient

time between reads. It is required of the system design and register access mechanisms to ensure the proper timing.

For example, multiple reads to the same register may occur faster than reads to different registers.

For 8 and 16-bit read cycles, the wait time for the back-to-back read operation is required only after the reading of the

last BYTE or WORD of the register, which completes a single DWORD transfer. There is no wait requirement between

the BYTE or WORD accesses within the DWORD transfer.

TABLE 5-3:

READ AFTER READ TIMING RULES

After reading...

wait for this many

nanoseconds...

or Perform this many

Reads of BYTE_TEST…

(assuming Tcyc of 45ns)

before reading...

Host MAC RX Data FIFO

135

RX FIFO Information Regis-

ter (RX_FIFO_INF)

Host MAC RX Status FIFO

135

RX FIFO Information Regis-

ter (RX_FIFO_INF)

Host MAC TX Status FIFO

135

TX FIFO Information Register

(TX_FIFO_INF)

Host MAC RX Dropped

Frames Counter Register

(RX_DROP)

180

Host MAC RX Dropped

Frames Counter Register

(RX_DROP)

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