LAN9250 datasheet(42/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 42

 2015 Microchip Technology Inc.

6.2.3

RESET REGISTERS

6.2.3.1

Reset Control Register (RESET_CTL)

This register contains software controlled resets.

Offset:

1F8h

Size:

32 bits

Note:

This register can be read while the device is in the reset or not ready / power savings states without leaving

the host interface in an intermediate state. If the host interface is in a reset state, returned data may be

invalid.

It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register.

Bits

Description

Type

Default

31:7

RESERVED

Host MAC Reset (HMAC_RST)

Setting this bit resets the Host MAC sub-system. When the Host MAC sub-

system is released from reset, this bit is automatically cleared. All writes to

this bit are ignored while this bit is set.

Note:

This bit is not accessible via the EEPROM Loader’s register

initialization function (Section 13.4.5).

R/W

RESERVED

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