LAN9250 datasheet(52/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 52

 2015 Microchip Technology Inc.

Wake On Status (WOL_STS)

This bit indicates that a Wake-Up, Magic Packet, Perfect DA, or Broadcast

frame was detected by the Host MAC.

In order to clear this bit, it is required that the event in the Host MAC be

cleared as well. The event sources are described in Section 6.3, "Power

Management," on page 44.

R/WC

RESERVED

PME Indication (PME_IND)

The PME signal can be configured as a pulsed output or a static signal,

which is asserted upon detection of a wake-up event. When set, the PME

signal will pulse active for 50mS upon detection of a wake-up event. When

cleared, the PME signal is driven continuously upon detection of a wake-up

event.

0: PME driven continuously on detection of event

1: PME 50mS pulse on detection of event

The PME signal can be deactivated by clearing the above status bit(s) or by

clearing the appropriate enable(s).

R/W

PME Polarity (PME_POL)

This bit controls the polarity of the PME signal. When set, the PME output is

an active high signal. When cleared, it is active low.

Note:

When PME is configured as an open-drain output, this field is

ignored and the output is always active low.

0: PME active low

1: PME active high

R/W

NASR

PME Enable (PME_EN)

When set, this bit enables the external PME signal pin. When cleared, the

external PME signal is disabled.

Note:

This bit does not affect the PME_INT interrupt bit of the Interrupt

Status Register (INT_STS).

0: PME pin disabled

1: PME pin enabled

R/W

Device Ready (READY)

When set, this bit indicates that the device is ready to be accessed. Upon

power-up, RST# reset, return from power savings states, Host MAC module

level reset or digital reset, the host processor may interrogate this field as an

indication that the device has stabilized and is fully active.

This rising edge of this bit will assert the Device Ready (READY) bit in

INT_STS and can cause an interrupt if enabled.

Note:

With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and

RESET_CTL registers, read access to any internal resources is

forbidden while the READY bit is cleared. Writes to any address

are invalid until this bit is set.

Note:

This bit is identical to bit 27 of the Hardware Configuration Register

(HW_CFG).

Bits

Description

Type

Default

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