LAN9250 datasheet(197/421 Pages) MICROCHIP

197 / 421 page

 2015 Microchip Technology Inc.

DS00001913A-page 197

LAN9250

11.15.2

HOST MAC ADDRESS HIGH REGISTER (HMAC_ADDRH)

This read/write register contains the upper 16-bits of the physical address of the Host MAC. The contents of this register

are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is

detected. The least significant byte of this register (bits [7:0]) is loaded from address 05h of the EEPROM. The second

byte (bits [15:8]) is loaded from address 06h of the EEPROM. Section 11.9, "Host MAC Address," on page 156 details

the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet phys-

ical address. Please refer to Section 13.4, "EEPROM Loader," on page 290 for more information on the EEPROM

Loader.

This register used to specify the address used for Perfect DA, Magic Packet and Wakeup frames, the unicast destination

address for received pause frames, and the source address for transmitted pause frames. This register is not used for

packet filtering.

Offset:

02h

Size:

32 bits

Bits

Description

Type

Default

31:16

RESERVED

15:0

Physical Address [47:32]

This field contains the upper 16-bits (47:32) of the Physical Address of the

Host MAC. The content of this field is undefined until loaded from the

EEPROM at power-on. The host can update the contents of this field after the

initialization process has completed.

R/W

FFFFh

LAN9250 bảng dữ liệu(PDF) 197 Page - Microchip Technology