TMS570LS0332PZ datasheet(88/110 Pages) TI1

88 / 110 page

TMS570LS0432, TMS570LS0332

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

www.ti.com

Table 7-14. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO

= output, and SPISOMI = input)(1)(2)(3)

NO.

PARAMETER

MIN

MAX UNIT

tc(SPC)M

Cycle time, SPICLK (4)

256tc(VCLK)

Pulse duration, SPICLK high (clock polarity

tw(SPCH)M

0.5tc(SPC)M – tr(SPC)M – 3

0.5tc(SPC)M + 3

= 0)

2(5)

Pulse duration, SPICLK low (clock polarity

tw(SPCL)M

0.5tc(SPC)M – tf(SPC)M – 3

0.5tc(SPC)M + 3

= 1)

Pulse duration, SPICLK low (clock polarity

tw(SPCL)M

0.5tc(SPC)M – tf(SPC)M – 3

0.5tc(SPC)M + 3

= 0)

3(5)

Pulse duration, SPICLK high (clock polarity

tw(SPCH)M

0.5tc(SPC)M – tr(SPC)M – 3

0.5tc(SPC)M + 3

= 1)

Valid time, SPICLK high after SPISIMO

tv(SIMO-SPCH)M

0.5tc(SPC)M – 6

data valid (clock polarity = 0)

4(5)

Valid time, SPICLK low after SPISIMO data

tv(SIMO-SPCL)M

0.5tc(SPC)M – 6

valid (clock polarity = 1)

Valid time, SPISIMO data valid after

tv(SPCH-SIMO)M

0.5tc(SPC)M – tr(SPC) – 4

SPICLK high (clock polarity = 0)

5(5)

Valid time, SPISIMO data valid after

tv(SPCL-SIMO)M

0.5tc(SPC)M – tf(SPC) – 4

SPICLK low (clock polarity = 1)

Setup time, SPISOMI before SPICLK high

tsu(SOMI-SPCH)M

tr(SPC) + 2.2

(clock polarity = 0)

6(5)

Setup time, SPISOMI before SPICLK low

tsu(SOMI-SPCL)M

tf(SPC) + 2.2

(clock polarity = 1)

Valid time, SPISOMI data valid after

tv(SPCH-SOMI)M

SPICLK high (clock polarity = 0)

7(5)

Valid time, SPISOMI data valid after

tv(SPCL-SOMI)M

SPICLK low (clock polarity = 1)

0.5*tc(SPC)M +

CSHOLD = 0

(C2TDELAY+2) * tc(VCLK) -

Setup time CS active until

tf(SPICS) + tr(SPC) – 7

tf(SPICS) + tr(SPC) + 5.5

SPICLK high (clock polarity

0.5*tc(SPC)M +

= 0)

CSHOLD = 1

(C2TDELAY+3) * tc(VCLK) -

tf(SPICS) + tr(SPC) – 7

tf(SPICS) + tr(SPC) + 5.5

8(6)

tC2TDELAY

0.5*tc(SPC)M +

CSHOLD = 0

(C2TDELAY+2) * tc(VCLK) -

Setup time CS active until

tf(SPICS) + tf(SPC) – 7

tf(SPICS) + tf(SPC) + 5.5

SPICLK low (clock polarity

0.5*tc(SPC)M +

= 1)

CSHOLD = 1

(C2TDELAY+3) * tc(VCLK) -

tf(SPICS) + tf(SPC) – 7

tf(SPICS) + tf(SPC) + 5.5

T2CDELAY*tc(VCLK) +

Hold time SPICLK low until CS inactive

tc(VCLK) - tf(SPC) + tr(SPICS) -

tc(VCLK) - tf(SPC) + tr(SPICS) +

(clock polarity = 0)

9(6)

tT2CDELAY

T2CDELAY*tc(VCLK) +

Hold time SPICLK high until CS inactive

tc(VCLK) - tr(SPC) + tr(SPICS) -

tc(VCLK) - tr(SPC) + tr(SPICS) +

(clock polarity = 1)

(C2TDELAY+1)* tc(VCLK) -

tSPIENA

SPIENAn Sample Point

(C2TDELAY+1)*tc(VCLK)

tf(SPICS) – 29

tSPIENAW

SPIENAn Sample point from write to buffer

(C2TDELAY+2)*tc(VCLK)

(1)

The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2)

tc(VCLK) = interface clock cycle time = 1 / f(VCLK)

(3)

For rise and fall timings, see the Table 5-6.

(4)

When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.

The external load on the SPICLK pin must be less than 60 pF.

(5)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6)

C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

Peripheral Information and Electrical Specifications

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